This makes it possible to predict, already during simulation, the performance of nonlinear devices such as power amplifiers with active linearization. Direct DPD can be used to predict how the performance of an RF amplifier can be improved by applying sophisticated linearization. This model can be used for subsequent real-time implementation on the target system. Cadence VSS software is made for system level design at various scales.
Some hardware implementations may become available earlier than others. Home Applications. From electronic design automation EDA to hardware implementation Linking EDA design simulation and hardware testing to enable an easy, straightforward process flow and first-pass design.
Referring back to Figure 5, note that the match for maximum power transfer does not correspond to the match for optimal PAE. A tradeoff will need to be made when the nonlinear aspects of the design are considered, but at this point, we have achieved design closure in the small signal by completing the small-signal design criteria, namely the match that we would like.
It will be very tempting to boost the PAE in ways that undermine the stability of the design—after all, what better way to get more power out with the same DC power than to create an oscillator!
But this is also an ideal step to expand the consideration of what actually comprises the input and output matching networks to include bias lines, grounding, and bondwires or bumps that are off- and on-chip.
Typically, bounds on parasitic source inductance are monitored to give guidance to layout bound-pad number and placement and packaging bondwire count and length in regard to not only degradation of the nonlinear performance criteria, but also to assuring that the requirements associated with the previous substeps are still being met.
The focus of this design step is to try to push out the compression of the linear output power as the input power is ramped up, as well as to boost the PAE. It can be tempting to change the FET periphery, but this can be dangerous, especially if load-pull has been involved, since the linear part of the design has presumably been optimized based on a detailed understanding of the FET input and output impedances.
If the IQ from 3 can be backed off to boost PAE without jeopardizing linearity, then some thermal margin of sorts is created with the lower current. One note should be emphasized in regard to FET modeling. If the testbench style of project organization Figure 8 has been done, the AWR Microwave Office nonlinear simulations can be reused with linear analysis simply by changing the measurement being performed on the testbench—ports in AWR software even nonlinear source ports act as S-parameter terminations so dual use can be obtained from a graph.
Furthermore, if the PA is Class C or better, the designer can start using transient analysis with this same simulation set up at the testbench schematic level. Figure 8. Testbench style of project development where the subcircuit is shared among left linear and right nonlinear analyses to ensure consistent capture of parametric design and design closure criteria.
For this particular design example, the nonlinear measurements of importance are the PAE as well as the gain compression Figure 9. If this particular FET size and bias are used with the conjugate match for maximum power transfer, then the PA compresses at lower output powers and it does not deliver the optimal PAE.
This can be understood from the load-pull contours in Figure 5, since the intersection of the conjugate S22 match with the load-pull results for this bias point show that the PA will not achieve the PAE maximum. The load-pull contours at this bias clearly show that both cannot be achieved simultaneously. In practice it is more often the case that the PA design will demand the conjugate matching of the transistor at the expense of PAE. In this case, the load-pull would have been relative to maximum power transfer and not to PAE.
Having completed the electrical design, the final design step is to actually lay out the PA. The parametric design requirement is somewhat lost at this point if the interconnects are not captured on the schematic, so, to the greatest degree possible, microstrip or coplanar waveguide elements should be placed on the schematic so that lengths and widths can be tied to maintaining the overall chip performance criteria.
Design closure is achieved when the nominal simulations, including all these effects, confirm that the overall chip performance criteria have been met. Small less than chip scale EM analysis can be done locally to confirm that the input and output matching networks achieve their desired performance, such as that defined by equation 5.
Using EXTRACT technology along the lines of the circuit partitioning that would normally be done—input match, FET stage s , and output match—enables the user to quickly confirm post-layout performance with schematic-based estimates from earlier in the design. Figure The resulting PAE and Pout simulation is also shown exhibiting the nonlinear performance degradation induced by these relatively minor but necessary features.
In contrast, the bond pads themselves Figure 11 offer very little change. Nonlinear performance of the ideal PA compared to adding three parallel bond pads at the PA output. The final analysis step is where the design assumptions and simplification taken while creating the design can be revisited in the context of the whole design now that it is seemingly complete.
This step enables the designer to ensure that the whole is at least the sum of the parts and that in the process of focusing on parts of the design i. The performance criteria are the overall chip requirements and design closure is achieved when the performance criteria are met relative to what that analysis explores: electrical performance for EM, reliability for thermal, manufacturability for DRC, etc.
An analysis step is performed to ensure that second-order effects like EM coupling and thermal do not violate earlier design parametric constraints and assumptions. EM analysis will verify assumptions on source inductance and interconnect parasitics that can contribute to feedback paths, which may enhance instabilities. Although time consuming and requiring memory-hungry workstations, the greater the detail of the EM analysis, the greater the likelihood of finding potential oscillations or performance-starving parasitic effects.
Going back and forth between the two is a great strategy for isolating any problems uncovered at this time. Formalized finite-element method FEM thermal analysis reconfirms the channel operating temperatures. Although new and different from the other substeps with which an electrical engineer may be familiar, thermal analysis is just too simple within the MMIC toolset and the payback too great NOT to do it.
Underpinning many of the assumptions of the PA design is the operating temperature of the FET channel. With all the metallization in place after the layout is finalized, an electrothermal analysis can reaffirm decisions made about FET channel spacing and DC bias.
Should either the EM or thermal verification step fail by not achieving design closure, then interconnects can be made wider or shorter to minimize inductance or spaced further apart to avoid capacitance, or pHEMT fingers can be spaced further apart to relieve channel heating. In short, and without trivializing, for the GaAs pHEMT PA designer, the thermal consideration can in many cases be a secondary effect handled as an analysis step during verification.
Of course, this is not withstanding aggressive thermal specifications or reliability requirements. The concern in this step is that the designer may actually succeed in finding a problem with the design. Since the design parameters have been abstracted away, the designer runs the risk of not knowing what to fix i. The analysis tools will indicate that there is a problem, but without the ability to directly tie cause and effect through parametric models, the best guide is experience.
Last but certainly not least, design-to-manufacturing closure is needed: No design should be shipped without foundry-based DRC. Moving from one technology to another requires that certain skills and knowledge be transportable and transferable. In particular, PA designers need a strategy, design flow, and guidelines for how to start with specifications and a PDK and get to a point where the more compli- cated design requirements can be tackled.
III-V semiconductor devices offer superior RF performance for mobile devices, communications infrastructure, and aerospace applications. Achieving optimal performance requires reliable circuit simulation, EM verification, communication test benches, and a design flow that links electrical design to physical realization.
AWR software offers a leading front-to-back monolithic microwave integrated circuit MMIC design flow with an innovative user interface and complete integration of design entry, simulation, and physical design tools that enhance engineering productivity and ensures first-pass success. The demand for wireless connected devices is driving the need for a new generation of high-performance, cost-sensitive silicon products. Skip to main content. Explore AWR. Automation Built on Experience Design-flow automation connects simulation models, third-party tools, and layout to manufacturing processes, from early concept exploration through engineering signoff.
The software has a user friendly interface that enables designers to have full control of the tool. Solve Your Toughest Design Challenges. Amplifiers Address your bandwidth, efficiency, and linearity challenges head-on with advanced harmonic-balance simulation as well as powerful load-pull analysis and impedance-matching circuit synthesis.
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